This invention relates to fabricating methods for semiconductor packages, and more particularly, to a fabricating method for a semiconductor package with a heat sink so as to improve the heat-dissipating efficiency.
A conventional semiconductor package having a semiconductor chip encapsulated by an encapsulant is concerned with efficient dissipation of heat generated by the chip during operation, so as to assure the lifetime and quality of the semiconductor package.
However, as the encapsulant for enclosing the semiconductor chip is made of a molding compound e.g. epoxy resin that is poor in thermal conductivity, the heat generated by the chip is unable to be effectively dissipated through the encapsulant. Accordingly, a metallic heat sink or heat block is incorporated in the semiconductor package for improving the heat-dissipating efficiency. However, it is undesirable if the heat sink is entirely encapsulated by the encapsulant, in which the generated heat still needs to pass through the encapsulant for dissipation, limiting the improvement in the heat-dissipating efficiency. Therefore, it is preferable to construct a semiconductor package having a surface of the heat sink exposed to the atmosphere, allowing the generated heat to be directly dissipated through the exposed surface. Nevertheless, if the heat sink is not in direct contact with the chip, while the molding compound is filled in a space between the heat sink and the chip, the heat dissipation will be undesirably impeded due to the heat generated by the chip unable to be effectively transmitted to the heat sink.
Thus, U.S. Pat. Nos. 5,726,079 and 5,471,366 respectively disclose a semiconductor package illustrated in FIG. 8. The semiconductor package 1 has a heat sink 11 directly attached to a chip 10, while a top surface 110 of the heat sink 11 is exposed to the outside of an encapsulant 12 used for encapsulating the chip 10. With the direct contact between the chip 10 and the heat sink 11, and between the exposed top surface 110 of the heat sink 11 and the atmosphere, heat generated by the chip 10 can be directly transmitted to the heat sink 11 for dissipation without passing through the encapsulant 12. This makes the semiconductor package 1 have better heat-dissipating efficiency than the one as previously recited.
Nevertheless, some drawbacks have been found for the semiconductor package 1 in fabrication. First, while the chip 10 together with the heat sink 11 are placed in a mold cavity in a molding process, the top surface 110 of the heat sink 11 should closely abut a top wall of the mold cavity for preventing a molding resin from flashing on the top surface 110 of the heat sink 11. Alternatively, if there is a gap formed between the top surface 110 of heat sink 11 and the top wall of the mold cavity, resin flash occurs on the top surface 110 of the heat sink 11, making a fabricated product deteriorated in profile and in heat-dissipating efficiency, and subsequently a deflash process is definitely required. However, the flash process is undesirably time-consuming and cost-ineffective, even possibly causing damage to the fabricated product. On the other hand, if the heat sink 11 abuts the top wall of the mold cavity too closely, excessive clamping force from the mold cavity will crack the fragile chip 10 beneath the heat sink 11.
Furthermore, an adhesive or laminating tape used in the attachment of the heat sink 11 to the chip 10 is usually made of a thermosetting material, which remains soft before being heated for curing. This makes the structure of the chip 10 combined with the heat sink 11 not precisely controlled in height, thus inducing the foregoing problem of the top surface 110 of the heat sink 11 not appropriately abutting the top wall of the mold cavity. As a result, the fabricated product can not be assured in quality as well as not cost-effective in fabrication.
Furthermore, due to lack of preciseness in the height controlling as mentioned above, the attachment of the heat sink 11 to the chip 10 can not be accomplished in a batch-type manner in the molding process for the semiconductor package 1. That is, the heat sink 11 must be attached to its corresponding chip 10 one by one. This obviously increases the complexity and time consumption for the molding process.
In addition, the heat-dissipating efficiency of the semiconductor package 1 is proportional to the exposed surface area of the heat sink 11. That is, with the semiconductor package 1 remained constant m dimension, the heat sink 11 can be made to maximize the exposed surface area for providing optimal heat-dissipating efficiency. However, in the case of the heat sink is dimensioned to be identical in surface area to the semiconductor package, if the heat sink is not precisely made, the heat sink can not be placed into the mold cavity properly when the heat sink is over-sized; while resin flash tends to occur on the top surface and side surfaces of the heat sink when the heat sink is insufficiently dimensioned.
A primary objective of the present invention is to provide a fabricating method for a semiconductor package, in which a heat sink is incorporated in the semiconductor package and dimensioned to maximize an exposed surface area thereof, so as to prevent resin flash from occurrence and improve the heat-dissipating efficiency. Moreover, the semiconductor package fabricated by the fabricating method of the invention allows the heat sink to come in direct contact with a chip for further improving the heat-dissipating efficiency, and also prevents the chip from cracking in a molding process for assuring quality of the package. Furthermore, the invention can be implemented with the heat sink being attached to the chip in a batch-type manner in no concern with height controlling, which makes the overall fabrication simplified in process and reduced in cost. In addition, molds used in the fabricating method of the invention can also be applied to various sized products, further reducing the fabrication cost.
In accordance with the above and other objectives, a fabricating method for a semiconductor package is proposed in the present invention, comprising the steps of: providing a matrix type chip carrier module plate consisting of a plurality of array-arranged chip carriers, wherein the chip carriers each has an upper surface and a lower surface; mounting at least one chip at a predetermined position on the upper surface of each of the chip carriers, and electrically connecting the chip to the chip carrier; providing a heat sink module plate having an upper surface and a lower surface, and attaching the lower surface of the heat sink module plate to the chips for interposing the chips between the chip carrier module plate and the heat sink module plate, wherein an interface layer is formed on the upper surface of the heat sink module plate, allowing adhesion between the interface layer and a molding compound to be smaller than that between the heat sink module plate and the molding compound; forming an encapsulant by the molding compound for encapsulating the heat sink module plate, the chips and the chip carrier module plate; performing a singulation process for forming individual semifabricated semiconductor packages corresponding in number to the plurality of chip carriers; and removing the molding compound formed on the interface layer so as to complete the fabrication of the semiconductor package.
The combined structure of the heat sink module plate, the chip and the chip carrier module plate has a height smaller than that of a mold cavity of a mold used in a molding process, in order to allow the molding compound to encapsulate the interface layer on the heat sink module plate upon completion of the molding process. As the interface layer has poor adhesion to the molding compound, the molding compound on the interface layer can be easily removed after the singulation process, which will not lead to delamination between a heat sink (formed by singulating the heat sink module plate) and the encapsulant due to good adhesion therebetween. Furthermore, as the heat sink module plate does not abut a top wall of the mold cavity, there is no concern for the chip to be cracked by the pressure from the mold via the heat sink module plate during molding. In addition, due to certain extent in flexibility for the height of the above combined structure, the mold can be applied to various kinds of semiconductor packages varied in height.
The interface layer on the heat sink can be made of a metallic material having poor adhesion to the molding compound for forming the encapsulant, such as gold, chromium, nickel, alloy thereof, or Teflon, making the heat dissipation through the heat sink not undesirably affected by the interface layer.
In a preferred embodiment of the invention, the chip carrier is a BGA (ball grid array) substrate, in which at least one hole is formed on the substrate, allowing bonding wires to pass through the hole for electrically connecting the substrate to the chip. On a surface of the substrate opposing that for mounting the chip thereon there are implanted a plurality of solder balls, which are used to electrically connect the chip to an external device.
In another preferred embodiment of the invention, the chip carrier is a flip chip substrate, that is, on an upper surface of the substrate there are formed a plurality of array-arranged solder pads for bonding a plurality of solder bumps thereto, while the solder bumps are used to electrically connect the chip to the substrate. Moreover, on a lower surface of the substrate there are implanted a plurality of solder balls for electrically connecting the chip to an external device.
In a further preferred embodiment of the invention, the chip carrier is a QFN (quad flat nonlead) lead frame or a BGA substrate, which has an upper surface for mounting the chip thereon and is connected to the chip through a plurality of bonding wires. In order to prevent the bonding wires from being damaged by the attachment of the heat sink to the chip, on the first surface of the heat sink there is formed a connecting portion extending toward the chip at a position corresponding to the chip. This allows the heat sink to be connected to the chip through the connecting portion without contacting the bonding wires.
In a further preferred embodiment of the invention, the chip carrier is a QFN lead frame or a BGA substrate, which has an upper surface for mounting the chip thereon and is connected to the chip through a plurality of bonding wires. In order to prevent the bonding wires from being damaged by the attachment of the heat sink to the chip, as well as reduce a thermal stress generated from the heat sink to the chip due to the difference in CTE (coefficient of thermal expansion) between the heat sink and the chip, a buffer pad having a similar CTE to that of the chip can be interposed between the heat sink and the chip. The buffer pad is preferable a defective die for optimizing the reduction in the thermal stress.
In addition, the first surface of the heat sink can be roughened, corrugated or made uneven so as to enhance the bonding strength between the heat sink and the encapsulant.